MOS FET. uPA2755AGR Datasheet

uPA2755AGR FET. Datasheet pdf. Equivalent

uPA2755AGR Datasheet
Recommendation uPA2755AGR Datasheet
Part uPA2755AGR
Description SWITCHING N-CHANNEL POWER MOS FET
Feature uPA2755AGR; DATA SHEET MOS FIELD EFFECT TRANSISTOR μ PA2755AGR SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION Th.
Manufacture Renesas
Datasheet
Download uPA2755AGR Datasheet




Renesas uPA2755AGR
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ PA2755AGR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The μ PA2755AGR is Dual N-channel MOS Field Effect
Transistor designed for DC/DC converters and power
management applications of notebook computers.
FEATURES
Dual chip type
Low on-state resistance
RDS(on)1 = 18 mΩ MAX. (VGS = 10 V, ID = 4.0 A)
RDS(on)2 = 29 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A)
Low input capacitance
Ciss = 650 pF TYP.
Built-in G-S protection diode
Small and surface mount package (Power SOP8)
PACKAGE DRAWING (Unit: mm)
85
14
5.37 MAX.
1 : Source 1
2 : Gate 1
7, 8: Drain 1
3 : Source 2
4 : Gate 2
5, 6: Drain 2
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
30 V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20 V
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
Total Power Dissipation (1 unit) Note2
Total Power Dissipation (2 units) Note2
ID(DC)
ID(pulse)
PT
PT
±8.0 A
±32 A
1.7 W
2.0 W
Channel Temperature
Tch 150 °C
Storage Temperature
Single Avalanche Current Note3
Single Avalanche Energy Note3
Tstg 55 to +150 °C
IAS 8 A
EAS 6.4 mJ
Notes 1. PW 10 μs, Duty Cycle 1%
2. Mounted on ceramic substrate of 2000 mm2 x 2.2 mm
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 0 V
EQUIVALENT CIRCUIT
(1/2 circuit)
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G19282EJ1V0DS00 (1st edition)
Date Published May 2008 NS
Printed in Japan
2008



Renesas uPA2755AGR
μ PA2755AGR
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
Zero Gate Voltage Drain Current
IDSS VDS = 30 V, VGS = 0 V
Gate Leakage Current
Gate to Source Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
IGSS
VGS(off)
| yfs |
RDS(on)1
VGS = ±18 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 4.0 A
VGS = 10 V, ID = 4.0 A
1.5
2.8
Input Capacitance
RDS(on)2
Ciss
VGS = 4.5 V, ID = 4.0 A
VDS = 10 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 4.0 A
Rise Time
tr VGS = 10 V
Turn-off Delay Time
Fall Time
td(off)
tf
RG = 10 Ω
Total Gate Charge
Gate to Source Charge
QG VDD = 24 V
QGS
VGS = 10 V
Gate to Drain Charge
Body Diode Forward Voltage Note
Reverse Recovery Time
QGD
VF(S-D)
trr
ID = 8.0 A
IF = 8.0 A, VGS = 0 V
IF = 8.0 A, VGS = 0 V
Reverse Recovery Charge
Qrr di/dt = 100 A/μs
Note Pulsed
TYP.
5.7
14
21
650
150
98
12
16
38
8.0
13
2.2
3.8
0.84
17
8.2
MAX.
10
±10
2.5
18
29
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
ID
VDD
IAS
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG. RG
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off)
tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet G19282EJ1V0DS



Renesas uPA2755AGR
μ PA2755AGR
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
120
100
80
60
40
20
0
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - °C
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
Mounted on ceramic
2.4
substrate of
2000 mm2 × 2.2 mm
2 units
2.0
1 unit
1.6
1.2
0.8
0.4
0
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
100
ID( pusl e)
10 ID( DC)
PW = 100 μs
RDS( on ) Limit ed
1 (at VGS = 10 V)
Power Dissipation Limit ed
0.1 M ount ed on ceramic subst rate of
2000 mm2 x 2.2mm, 1unit
TA = 25°C
Single pulse
0.01
0.01 0.1
1
10
1 ms
10 ms
100 ms
DC
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
Rth(ch-A) = 73.5°C/W
10
1
Mounted on ceramic substrate of 2000 mm2 x 2.2 mm
Single pulse, 1 unit
TA = 25°C
0.1
100 μ
1m
10 m
100 m
1
PW - Pulse Width - s
10
100 1000
Data Sheet G19282EJ1V0DS
3







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