Mobile DDR. H9DP32A4JJBCGR-KEM Datasheet

H9DP32A4JJBCGR-KEM DDR. Datasheet pdf. Equivalent

H9DP32A4JJBCGR-KEM Datasheet
Recommendation H9DP32A4JJBCGR-KEM Datasheet
Part H9DP32A4JJBCGR-KEM
Description 4GB eNAND Flash(x8) + 4Gb Mobile DDR
Feature H9DP32A4JJBCGR-KEM; CI-MCP Specification 4GB eNAND Flash(x8) + 4Gb Mobile DDR (x32) This document is a general product .
Manufacture Hynix
Datasheet
Download H9DP32A4JJBCGR-KEM Datasheet




Hynix H9DP32A4JJBCGR-KEM
CI-MCP Specification
4GB eNAND Flash(x8)
+ 4Gb Mobile DDR (x32)
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 0.1 / Nov. 2012
1



Hynix H9DP32A4JJBCGR-KEM
Preliminary
H9DP32A4JJBCGR
eNAND 4GB(x8) / Mobile DDR 4Gb(x32, 2CS)
Document Title
CI-MCP
4GB(x8) eNAND Flash / 4Gb (x32) Mobile DDR
Revision History
Revision No.
History
0.1 - Initial Draft
0.2 - Updated DC and AC CHARACTERISTICS
Draft Date
Nov. 2012
Nov. 2012
Remark
Preliminary
Preliminary
Rev 0.1 / Nov. 2012
2



Hynix H9DP32A4JJBCGR-KEM
Preliminary
H9DP32A4JJBCGR
eNAND 4GB(x8) / Mobile DDR 4Gb(x32, 2CS)
FEATURES
[ CI-MCP ]
Operation Temperature
- (-25)oC ~ 85oC
Package
- 153-ball FBGA - 11.5x13.0mm2, 1.0t, 0.5mm pitch
- Lead & Halogen Free
[ e-NAND ]
[ DDR SDRAM ]
Packaged NAND flash memory with MultiMedia-
Card interface
e-NAND system specification, compliant with
V4.41
Full backward compatibility with previous e-
NAND system specification
Bus mode
- High-speed eMMC protocol.
- Three different data bus widths:
1 bit, 4 bits,8 bits.
- Data transfer rate: up to 104Mbyte/s
- DDR mode supported
Operating voltage range:
- VCCQ = 3.3/1.8V
- VCC = 3.3V
Error free memory access
- Internal error correction code
- Internal enhanced data management
algorithm (Wear levelling, Bad block
management, Garbage collection)
- Possibility for the host to make sudden power
failure safe-update operations for data content
Security
- Password protection of data
- Secure Erase
- Secure Trim
- Secure bad block management
- Write Protection
Boot
- Nomal / Alternative boot sequence method
Power saving
- Enhanced power saving method by
introducing sleep functionality
Partition management with enhanced storage.
Hardware reset supported
Double Data Rate architecture
- two data transfer per clock cycle
x32 bus width
Supply Voltage
- VDD / VDDQ = 1.7 - 1.95 V
Memory Cell Array
- 16Mb x 4Bank x 32 I/O
Bidirectional data strobe (DQS)
Input data mask signal (DQM)
Input Clock
- Differential Clock Inputs (CK, /CK)
MRS, EMRS
- JEDEC Standard guaranteed
CAS Latency
- Programmable CAS latency 2 or 3 supported
Burst Length
- Programmable burst length 2 / 4 / 8 with both sequential
and interleave mode
Rev 0.1 / Nov. 2012
3







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