Bring the SYNC line low to begin the write sequence. Data from
the SDI line is clocked into the 24-bit input shift register on the
falling edge of SCLK. After the last of 24 data bits is clocked in,
bring SYNC high. The programmed function is then executed,
that is, an LDAC-dependent change in DAC register contents
and/or a change in the mode of operation. If SYNC is taken
high at a clock before the 24th clock, it is considered a valid
frame, and invalid data is loaded to the DAC. Bring SYNC high
for a minimum of 20 ns (single channel, see t8 in Figure 2)
before the next write sequence so that a falling edge of SYNC
can initiate the next write sequence. Idle SYNC at rails between
write sequences for even lower power operation. The SYNC line
is kept low for 24 falling edges of SCLK, and the DAC is
updated on the rising edge of SYNC.
When data is transferred into the input register of the addressed
DAC, all DAC registers and outputs update by taking LDAC low
while the SYNC line is high.
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on LDAC)
Command 0001 allows the user to write the dedicated input
register of each DAC individually. When LDAC is low, the input
register is transparent, if not controlled by the LDAC mask
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers and outputs with the
contents of the input registers selected and updates the DAC
Write to and Update DAC Channel n (Independent of LDAC)
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly. Bit D7 to Bit D0
determine which DACs have data from the input register
transferred to the DAC register. Setting a bit to 1 transfers data
from the input register to the appropriate DAC register.
For systems that contain several DACs, the SDO pin can daisy-
chain several devices together and is enabled through a software
executable daisy-chain enable (DCEN) command. Command
1000 is reserved for this DCEN function (see Table 10). The
daisy-chain mode is enabled by setting Bit DB0 in the DCEN
register. The default setting is standalone mode, where DB0 = 0.
Table 12 shows how the state of the bit corresponds to the mode
of operation of the device.
Table 12. Daisy-Chain Enable (DCEN) Register
0 Standalone mode (default)
1 DCEN mode
Figure 62. Daisy-Chaining the AD5672R/AD5676R
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDI input on the next DAC in the chain, a daisy-chain interface is
constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of devices updated. If SYNC is
taken high at a clock that is not a multiple of 24, it is considered
a valid frame, and invalid data may be loaded to the DAC.
When the serial transfer to all devices is complete, SYNC goes
high, which latches the input data in each device in the daisy
chain and prevents any further data from being clocked into the
input shift register. The serial clock can be continuous or a gated
clock. If SYNC is held low for the correct number of clock
cycles, a continuous SCLK source is used. In gated clock mode,
use a burst clock containing the exact number of clock cycles,
and take SYNC high after the final clock to latch the data.
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