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CLOCK GENERATOR. SI52111-B5 Datasheet

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CLOCK GENERATOR. SI52111-B5 Datasheet






SI52111-B5 GENERATOR. Datasheet pdf. Equivalent




SI52111-B5 GENERATOR. Datasheet pdf. Equivalent





Part

SI52111-B5

Description

PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR



Feature


Si52111-B5/B6 PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR Features  P CI-Express Gen 1, Gen 2,  Triangula r spread spectrum Gen 3, and Gen 4 com mon clock profile for maximum EMI comp liant reduction (Si52111-B6)  Gen 3 SRNS Compliant  Extended Temperat ure:  Low power HCSL differential –40 to 85 °C output buffer  3.3 V Power supply  Supports Seria.
Manufacture

Silicon Laboratories

Datasheet
Download SI52111-B5 Datasheet


Silicon Laboratories SI52111-B5

SI52111-B5; l-ATA (SATA) at  Small package 10-pin TDFN 100 MHz (3x3 mm)  No termin ation resistors required  Si52111-B5 does not support  25 MHz Crystal I nput or Clock spread spectrum outputs input  Si52111-B6 supports 0.5% do wn spread outputs Applications  Ne twork Attached Storage  Multi-functi on Printer  Wireless Access Point Routers Description Si52111-B5/B.


Silicon Laboratories SI52111-B5

6 is a high-performance, PCIe clock gene rator that can source one PCIe clock ou tput from a 25 MHz crystal or clock inp ut. The clock output is compliant to PC Ie Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common clock specifications. The ultra-small footprint (3x3 mm) and indu stry leading low power consumption make Si52111-B5/B6 the ideal clock solution for consumer and .


Silicon Laboratories SI52111-B5

embedded applications. Measuring PCIe cl ock jitter is quick and easy with the S ilicon Labs PCIe Clock Jitter Tool. Dow nload it for free at www.silabs.com/pci e-learningcenter. Ordering Information : See page 13 Pin Assignments VDD 1 X OUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 NC 8 NC 7 DIFF1 6 DIFF1 Functional Bl ock Diagram Patents pending VDD XIN/ CLKIN XOUT Rev 1.2.

Part

SI52111-B5

Description

PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR



Feature


Si52111-B5/B6 PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR Features  P CI-Express Gen 1, Gen 2,  Triangula r spread spectrum Gen 3, and Gen 4 com mon clock profile for maximum EMI comp liant reduction (Si52111-B6)  Gen 3 SRNS Compliant  Extended Temperat ure:  Low power HCSL differential –40 to 85 °C output buffer  3.3 V Power supply  Supports Seria.
Manufacture

Silicon Laboratories

Datasheet
Download SI52111-B5 Datasheet




 SI52111-B5
Si52111-B5/B6
PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK
GENERATOR
Features
PCI-Express Gen 1, Gen 2,
Triangular spread spectrum
Gen 3, and Gen 4 common clock profile for maximum EMI
compliant
reduction (Si52111-B6)
Gen 3 SRNS Compliant
Extended Temperature:
Low power HCSL differential
–40 to 85 °C
output buffer
3.3 V Power supply
Supports Serial-ATA (SATA) at Small package 10-pin TDFN
100 MHz
(3x3 mm)
No termination resistors required Si52111-B5 does not support
25 MHz Crystal Input or Clock
spread spectrum outputs
input
Si52111-B6 supports 0.5% down
spread outputs
Applications
Network Attached Storage
Multi-function Printer
Wireless Access Point
Routers
Description
Si52111-B5/B6 is a high-performance, PCIe clock generator that can
source one PCIe clock output from a 25 MHz crystal or clock input. The
clock output is compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and
Gen 4 common clock specifications. The ultra-small footprint (3x3 mm)
and industry leading low power consumption make Si52111-B5/B6 the
ideal clock solution for consumer and embedded applications. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Ordering Information:
See page 13
Pin Assignments
VDD 1
XOUT 2
XIN/CLKIN 3
VSS 4
VSS 5
10 VDD
9 NC
8 NC
7 DIFF1
6 DIFF1
Functional Block Diagram
Patents pending
VDD
XIN/CLKIN
XOUT
Rev 1.2 12/15
PLL Divider
DIFF1
VSS
Copyright © 2015 by Silicon Laboratories
Si52111-B5/B6




 SI52111-B5
Si52111-B5/B6
2 Rev 1.2




 SI52111-B5
TABLE OF CONTENTS
Si52111-B5/B6
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1. Crystal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2. Calculating Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. 10-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. 8-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1. TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rev 1.2
3



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