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CLOCK GENERATOR. SI52112-B5 Datasheet

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CLOCK GENERATOR. SI52112-B5 Datasheet






SI52112-B5 GENERATOR. Datasheet pdf. Equivalent




SI52112-B5 GENERATOR. Datasheet pdf. Equivalent





Part

SI52112-B5

Description

PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR



Feature


Si52112-B5/B6 PCI-EXPRESS GEN 3 DUAL OU TPUT CLOCK GENERATOR Features  PCI -Express Gen 1, Gen 2,  Triangular spread spectrum Gen 3, and Gen 4 commo n clock profile for maximum EMI compli ant reduction (Si52112-B6)  Gen 3 SRNS Compliant  Extended Temperatur e:  Low power HCSL differential 40 to 85 °C output buffers  3.3 V Power supply  Supports Serial.
Manufacture

Silicon Laboratories

Datasheet
Download SI52112-B5 Datasheet


Silicon Laboratories SI52112-B5

SI52112-B5; -ATA (SATA) at  Small package 10-pin TDFN 100 MHz (3x3 mm)  No termina tion resistors required  Si52112-B5 does not support  25 MHz Crystal In put or Clock spread spectrum outputs input  Si52112-B6 supports 0.5% dow n spread outputs Applications  Net work attached storage  Multi-functio n printer  Wireless access point Routers Description Si52112-B5/B6.


Silicon Laboratories SI52112-B5

is a high-performance, PCIe clock gener ator that can source two PCIe clocks fr om a 25 MHz crystal or clock input. The clock outputs are compliant to PCIe Ge n 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common clock specifications. The ultra -small footprint (3x3 mm) and industry leading low power consumption make Si52 112-B5/B6 the ideal clock solution for consumer and embed.


Silicon Laboratories SI52112-B5

ded applications. Measuring PCIe clock j itter is quick and easy with the Silico n Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-lea rningcenter. Ordering Information: See page 13 Pin Assignments VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 DIFF2 8 DIFF2 7 DIFF1 6 DIFF1 Patents pendi ng Functional Block Diagram VDD XIN/ CLKIN XOUT PLL Di.

Part

SI52112-B5

Description

PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR



Feature


Si52112-B5/B6 PCI-EXPRESS GEN 3 DUAL OU TPUT CLOCK GENERATOR Features  PCI -Express Gen 1, Gen 2,  Triangular spread spectrum Gen 3, and Gen 4 commo n clock profile for maximum EMI compli ant reduction (Si52112-B6)  Gen 3 SRNS Compliant  Extended Temperatur e:  Low power HCSL differential 40 to 85 °C output buffers  3.3 V Power supply  Supports Serial.
Manufacture

Silicon Laboratories

Datasheet
Download SI52112-B5 Datasheet




 SI52112-B5
Si52112-B5/B6
PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR
Features
PCI-Express Gen 1, Gen 2,
Triangular spread spectrum
Gen 3, and Gen 4 common clock profile for maximum EMI
compliant
reduction (Si52112-B6)
Gen 3 SRNS Compliant
Extended Temperature:
Low power HCSL differential
–40 to 85 °C
output buffers
3.3 V Power supply
Supports Serial-ATA (SATA) at Small package 10-pin TDFN
100 MHz
(3x3 mm)
No termination resistors required Si52112-B5 does not support
25 MHz Crystal Input or Clock
spread spectrum outputs
input
Si52112-B6 supports 0.5% down
spread outputs
Applications
Network attached storage
Multi-function printer
Wireless access point
Routers
Description
Si52112-B5/B6 is a high-performance, PCIe clock generator that can
source two PCIe clocks from a 25 MHz crystal or clock input. The clock
outputs are compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and
Gen 4 common clock specifications. The ultra-small footprint (3x3 mm)
and industry leading low power consumption make Si52112-B5/B6 the
ideal clock solution for consumer and embedded applications. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Ordering Information:
See page 13
Pin Assignments
VDD 1
XOUT 2
XIN/CLKIN 3
VSS 4
VSS 5
10 VDD
9 DIFF2
8 DIFF2
7 DIFF1
6 DIFF1
Patents pending
Functional Block Diagram
VDD
XIN/CLKIN
XOUT
PLL Divider
DIFF1
DIFF2
VSS
Rev 1.2 12/15
Copyright © 2015 by Silicon Laboratories
Si52112-B5/B6




 SI52112-B5
Si52112-B5/B6
2 Rev 1.2




 SI52112-B5
TABLE OF CONTENTS
Si52112-B5/B6
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1. Crystal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2. Calculating Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. 10-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. 8-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1. TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rev 1.2
3



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