Low Voltage DDR Termination Regulator
Description
POWER MANAGEMENT
Features
Input to linear regulator (VIN): 1.0V to 3.6V Output (VTT): 0.5V to 1.8V Bias Voltage (VDD): 2.35V to 3.6V Up to 3A sink or source from VTT for DDR through
DDR4 + 1% over temperature (with respect to VDDQ/2, in-
cluding internal resistor divider variation) VREF and VTT Logic-level enable input Built in soft-start The...
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