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IS61QDB22M36

ISSI
Part Number IS61QDB22M36
Manufacturer ISSI
Description QUAD (Burst of 2) Synchronous SRAMs
Published Jun 10, 2016
Detailed Description 72 Mb (2M x 36. & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs A May 2009 Features • 2M x 36 or 4M x 18. • On-chip del...
Datasheet PDF File IS61QDB22M36 PDF File

IS61QDB22M36
IS61QDB22M36

Overview
72 Mb (2M x 36.
& 4M x 18) QUAD (Burst of 2) Synchronous SRAMs A May 2009 Features • 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Separate read and write ports with concurrent read and write operations.
• Synchronous pipeline read with early write operation.
• Double data rate (DDR) interface for read and write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and control registering at rising edges only.
• Two input clocks (C and C) for data output control.
• Two echo clocks (CQ and CQ) that are delivered simultaneously with data.
• +1.
8V core power supply and 1.
5, 1.
8V VDDQ, used with 0.
75, 0.
9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls, byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.
1 functions.
• Byte write capability.
• Fine ball grid array (FBGA) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array • Programmable impedance output drivers via 5x user-supplied precision resistor.
Description The 72Mb IS61QDB22M36 and IS61QDB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.
These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth Table on page 8 for a description of the basic operations of these SRAMs.
The input address bus operates at double data rate.
The following are registered internally on the rising edge of the K clock: • Read address • Read enable • Write enable • Byte writes • Data-in for early writes The following are registered on the rising edge of the K clock: • Write address • Byte writes • Data-in for second burst addresses Byte writes can change with the corresponding datain to enable or d...


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