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IS61QDB24M18

Part Number	IS61QDB24M18
Manufacturer	ISSI
Description	QUAD (Burst of 2) Synchronous SRAMs
Published	Jun 10, 2016
Detailed Description	72 Mb (2M x 36. & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs A May 2009 Features • 2M x 36 or 4M x 18. • On-chip del...
Datasheet	IS61QDB24M18 PDF File

Overview

72 Mb (2M x 36.
& 4M x 18) QUAD (Burst of 2) Synchronous SRAMs A May 2009 Features • 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Separate read and write ports with concurrent read and write operations.
• Synchronous pipeline read with early write operation.
• Double data rate (DDR) interface for read and write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and control registering at rising edges only.
• Two input clocks (C and C) for data output control.
• Two echo clocks (CQ and CQ) that are delivered simultaneously with data.
• +1.
8V core power supply and 1.
5, 1.
8V VDD...

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