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IS61VVPS51236B

Part Number	IS61VVPS51236B
Manufacturer	Integrated Silicon Solution
Description	SINGLE CYCLE DESELECT STATIC RAM
Published	Jul 25, 2016
Detailed Description	IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B 512K x36 and 1024K x18 18Mb SY...
Datasheet	IS61VVPS51236B PDF File

Overview

IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B 512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM AUGUST 2017 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages • Power supply: LPS: VDD 3.
3V (± 5%), VDDQ 3.
3V/2.
5V (± 5%) VPS: VDD 2.
5V (± 5%), VDDQ 2.
5V (± 5%) VVPS: VDD 1.
8V (± 5%), VDDQ 1.
8V (± 5%) • JTAG Boundary Scan for BGA packages • Commercial, Industrial and Automotive temperature support • Lead-free available • For leaded options, please contact ISSI FAST ACCESS TIME DESCRIPTION The 18Mb product family features high-speed, lowpower synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.
The IS61LPS/VPS/VVPS51236B are organized as 524,288 words by 36bits.
The IS61LPS/VPS/VVPS102418B are organized as 1,048,576 words by 18bits.
Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input.
Write cycles can be one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write enable (/BWE) input combined with one or more individual byte write signals (/BWx).
In addition, Globa...

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IS61VVPS51236B SINGLE CYCLE DESELECT STATIC RAM - Integrated Silicon Solution

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