IS61DDB24M18A IS61DDB22M36A
4Mx18, 2Mx36
72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
AUGUST 2014
FEATURES
2Mx36 and 4Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid
window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write
operation. Double Data Rate (DDR) interface for read and...