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IS61DDPB251236A2

Part Number	IS61DDPB251236A2
Manufacturer	Integrated Silicon Solution
Description	18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
Published	Jul 25, 2016
Detailed Description	IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 1Mx18, 512Kx36 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Lat...
Datasheet	IS61DDPB251236A2 PDF File

Overview

IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 1Mx18, 512Kx36 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.
5 Cycle Read Latency) ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Common I/O read and write ports.
 Synchronous pipeline read with self-timed late write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 2.
5 cycle read latency.
 Fixed 2-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
 +1.
8V core power supply and 1.
5, 1.
8V VDDQ, used with 0.
75, 0.
9V VREF.
 HSTL input and output interface.
 Registered addresses, write and read controls, byte writes, data in, and data outputs.
 Full data coherency.
 Boundary scan using limited set of JTAG 1149.
1 functions.
...

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