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GS81314LD37GK

GSI Technology
Part Number GS81314LD37GK
Manufacturer GSI Technology
Description 144Mb SigmaQuad-IVe Burst of 4 Single-Bank ECCRAM
Published Oct 13, 2016
Detailed Description GS81314LD19/37GK-933/800 260-Pin BGA Com & Ind Temp HSTL I/O 144Mb SigmaQuad-IVe™ Burst of 4 Single-Bank ECCRAM™ Up t...
Datasheet PDF File GS81314LD37GK PDF File

GS81314LD37GK
GS81314LD37GK

Overview
GS81314LD19/37GK-933/800 260-Pin BGA Com & Ind Temp HSTL I/O 144Mb SigmaQuad-IVe™ Burst of 4 Single-Bank ECCRAM™ Up to 933 MHz 1.
2V ~ 1.
3V VDD 1.
2V ~ 1.
3V VDDQ Features • 4Mb x 36 and 8Mb x 18 organizations available • Organized as a single logical memory bank • 933 MHz maximum operating frequency • 933 MT/s peak transaction rate (in millions per second) • 134 Gb/s peak data bandwidth (in x36 devices) • Separate I/O DDR Data Buses • Non-multiplexed SDR Address Bus • One operation - Read or Write - per clock cycle • No address/bank restrictions on Read and Write ops • Burst of 4 Read and Write operations • 5 cycle Read Latency • On-chip ECC with virtually zero SER • Loopback signal timing training capability • 1.
2V ~ 1.
3V nominal core voltage • 1.
2V ~ 1.
3V HSTL I/O interface • Configuration registers • Configurable ODT (on-die termination) • ZQ pin for programmable driver impedance • ZT pin for programmable ODT impedance • IEEE 1149.
1 JTAG-compliant Boundary Scan • 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- compliant BGA package SigmaQuad-IVe™ Family Overview SigmaQuad-IVe ECCRAMs are the Separate I/O half of the SigmaQuad-IVe/SigmaDDR-IVe family of high performance ECCRAMs.
Although similar to GSI's third generation of networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe family), these fourth generation devices offer several new features that help enable significantly higher performance.
Clocking and Addressing Schemes The GS81314LD19/37GK SigmaQuad-IVe ECCRAMs are synchronous devices.
They employ three pairs of positive and negative input clocks; one pair of master clocks, CK and CK, and two pairs of write data clocks, KD[1:0] and KD[1:0].
All six input clocks are single-ended; that is, each is received by a dedicated input buffer.
CK and CK are used to latch address and control inputs, and to control all output timing.
KD[1:0] and KD[1:0] are used solely to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B4 ECCRAM is four t...


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