High-performance Electrically Erasable Programmable Logic Device
Description
Features
Industry-standard Architecture 12ns Maximum Pin-to-pin Delay Zero Power – 100µA Maximum Standby Power (Input Transition Detection) CMOS and TTL Compatible Inputs and Outputs Advanced Electrically ErasableTechnology
– Reprogrammable – 100% Tested Latch Feature Holds Inputs to Previous Logic State High-reliability CMOS Process – 20 Year ...
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