1.8V Synchronous Pipelined SRAM
Description
CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18
72-Mbit DDR-II SRAM 4-Word Burst Architecture
Features
Functional Description
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) 300-MHz clock for high bandwidth 4-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz Two input cloc...
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