36-Mbit DDR II+ SRAM Two-Word Burst Architecture
Description
CY7C1268KV18/CY7C1270KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ 36-Mbit density (2 M × 18, 1 M × 36) ■ 550 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transfer...
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