72-Mbit DDR II+ SRAM Two-Word Burst Architecture
Description
CY7C1568KV18/CY7C1570KV18
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ 72-Mbit density (4M × 18, 2M × 36) ■ 550 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferre...
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