DatasheetsPDF.com

CY7C1570KV18

Part Number	CY7C1570KV18
Manufacturer	Cypress Semiconductor
Description	72-Mbit DDR II+ SRAM Two-Word Burst Architecture
Published	Mar 14, 2017
Detailed Description	CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit DDR II+ SRA...
Datasheet	CY7C1570KV18 PDF File

Overview

CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.
5 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.
5 Cycle Read Latency) Features ■ 72-Mbit density (4M × 18, 2M × 36) ■ 550 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.
5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ operates ...

Similar Datasheet

CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture - Cypress Semiconductor

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)