36-Mbit QDR II SRAM Two-Word Burst Architecture
Description
CY7C1425KV18 CY7C1412KV18 CY7C1414KV18
36-Mbit QDR® II SRAM Two-Word Burst Architecture
36-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) Interfaces on both read and write po...
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