CPLD
Description
Features
High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 15 ns Maximum Pin-to-pin Delay for 5V Operation 24 Flexible Output Macrocells
– 48 Flip-flops – Two per Macrocell – 72 Sum Terms – All Flip-flops, I/O Pins Feed in Independently D- or T-type Flip-flops Produc...
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