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DF011

AMI
Part Number DF011
Manufacturer AMI
Description CMOS Gate Array
Published Mar 12, 2018
Detailed Description Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF011 is a static, master-slave D flip-flop. RESET i...
Datasheet PDF File DF011 PDF File

DF011
DF011

Overview
Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF011 is a static, master-slave D flip-flop.
RESET is asynchronous and active low.
Output is unbuffered and changes state on the rising edge of the clock.
Logic Symbol Truth Table Pin Loading DF011 DQ C R RN D C Q LXXL HL ↑L HH ↑H H X L NC NC = No Change Equivalent Load D 1.
0 C 1.
0 RN 1.
0 Equivalent Gates .
8.
0 HDL Syntax Verilog DF011 inst_name (Q, C, D, RN); VHDL.
.
inst_name: DF011 port map (Q, C, D, RN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation.
Value TBD 17.
8 Units nA Eq-load Propagation Delay...


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