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DF101

AMI
Part Number DF101
Manufacturer AMI
Description CMOS Gate Array
Published Mar 12, 2018
Detailed Description Core Logic ')[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF10x is a family of static, master-slave D flip-flo...
Datasheet PDF File DF101 PDF File

DF101
DF101

Overview
Core Logic ')[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF10x is a family of static, master-slave D flip-flops.
SET is asynchronous and active low.
Outputs are buffered and change state on the rising edge of the clock.
Logic Symbol Truth Table DF10x DSQ C Q SN D C Q QN L XXH L HL ↑ LH HH ↑H L H X L NC NC NC = No Change HDL Syntax Verilog.
.
.
.
DF10x inst_name (Q, QN, C, D, SN); VHDL.
.
inst_name: DF10x port map (Q, QN, C, D, SN); Pin Loading Pin Name D C SN DF101 1.
0 1.
0 2.
1 Equivalent Loads DF102 DF104 1.
0 1.
0 1.
0 1.
0 2.
1 3.
2 DF106 1.
0 1.
0 3.
2 Size And Power Characteristics Cell Equivalent Gates Power Characteristicsa Static IDD (...


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