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ODTXXE02

Part Number	ODTXXE02
Manufacturer	AMI
Description	CMOS Gate Array
Published	Mar 13, 2018
Detailed Description	2'7;;([[ ® $0,+* PLFURQ &026 *DWH $UUD\ Description ODTXXExx is a family of 1 to 24 mA, non-inverting, TTL-level...
Datasheet	ODTXXE02 PDF File

Overview

2'7;;([[ ® $0,+* PLFURQ &026 *DWH $UUD\ Description ODTXXExx is a family of 1 to 24 mA, non-inverting, TTL-level, tristate output buffer pieces with active low enables.
Logic Symbol Truth Table ODTXXExx EN A PADM EN A PADM LL L LH H HX Z Z = High Impedance HDL Syntax Verilog ODTXXExx inst_name (PADM, A, EN); VHDL.
.
inst_name: ODTXXExx port map (PADM, A, EN); Pin Loading Pin Name A (eq-load) EN (eq-load) PADM (pF) ODTXXE01 5.
6 4.
0 4.
92 ODTXXE02 7.
9 5.
3 4.
92 ODTXXE04 7.
9 5.
3 4.
93 Load ODTXXE08 2.
3 5.
5 4.
93 ODTXXE12 2.
3 5.
5 4.
93 ODTXXE16 2.
3 5.
5 4.
93 ODTXXE24 2.
3 5.
5 4.
93 Power Characteristics Cell Output Drive (mA) ODTXX...

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