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M14D128168A

Part Number	M14D128168A
Manufacturer	ESMT
Description	DDR-II SDRAM
Published	Sep 20, 2018
Detailed Description	ESMT DDR II SDRAM M14D128168A (2Y) 2M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ ...
Datasheet	M14D128168A PDF File

Overview

ESMT DDR II SDRAM M14D128168A (2Y) 2M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.
8V ± 0.
1V, VDDQ = 1.
8V ± 0.
1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition 1KB page size - Row address: A0 to A11 - Column address: A0 to A8 Quad bank operation CAS Latency : 3, 4, 5, 6, 7 Additive Latency: 0, 1, 2, 3, 4, 5, 6 Burst Type : Sequential and Interleave Burst Length : 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only Off-Chip-Driver (OCD) impedance adjustment On-Die-Termination for better signal quality Special fun...

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M14D128168A DDR-II SDRAM - ESMT

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