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M15T2G16128A

ESMT
Part Number M15T2G16128A
Manufacturer ESMT
Description DDR3 SDRAM
Published Sep 20, 2018
Detailed Description ESMT (Preliminary) M15T2G16128A (2L) DDR3(L) SDRAM Feature Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.0...
Datasheet PDF File M15T2G16128A PDF File

M15T2G16128A
M15T2G16128A

Overview
ESMT (Preliminary) M15T2G16128A (2L) DDR3(L) SDRAM Feature Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.
5V(±0.
075V) ˗ SSTL_135: VDD/VDDQ = 1.
35V(-0.
067V/+0.
1V) JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM Data Integrity ˗ Auto Self Refresh (ASR) by DRAM built-in TS ˗ Auto Refresh and Self Refresh Modes Power Saving Mode ˗ Power Down Mode Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy 16M x 16 Bit x 8 Banks DDR3(L) SDRAM via external ZQ pad (240 ohm ± 1%) Signal Synchronization 1 ˗ Write L...


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