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74LVC373A-Q100

Part Number	74LVC373A-Q100
Manufacturer	nexperia
Description	Octal D-type transparent latch
Published	Jul 29, 2019
Detailed Description	74LVC373A-Q100 Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 3 — 4 March 2021 Produc...
Datasheet	74LVC373A-Q100 PDF File

Overview

74LVC373A-Q100 Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev.
3 — 4 March 2021 Product data sheet 1.
General description The 74LVC373A-Q100 is an octal D-type transparent latch with 3-state outputs.
The device features latch enable (LE) and output enable (OE) inputs.
When LE is HIGH, data at the inputs enter the latches.
In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Operation of the OE input does not affect the state of the latches.
Inputs can be driven from either 3.
3 V or 5 V devices.
This feature allows the use of these devices as translators in mixed 3.
3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF.
The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2.
Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Overvoltage tolerant inputs to 5.
5 V • Wide supply voltage range from 1.
2 V to 3.
6 V • CMOS low power consumption • Direct interface with TTL levels • High-impedance outputs when VCC = 0 V • IOFF circuitry provides partial Power-down mode operation • Complies with JEDEC standard: • JESD8-7A (1.
65 V to 1.
95 V) • JESD8-5A (2.
3 V to 2.
7 V) • JESD8-C/JESD36 (2.
7 V to 3.
6 V) • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000...

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74LVC373A-Q100 Octal D-type transparent latch - nexperia

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