TMS626162A
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS692B – JULY 1997 – REVISED MARCH 1998
D Organization
512K × 16 Bits × 2 Banks
D 3.3-V Power Supply (± 10% Tolerance) D Two Banks for On-Chip Interleaving
(Gapless Accesses)
D High Bandwidth – Up to 100-MHz Data
Rates
D CAS Latency (CL) Programmable to Two or
Three Cycles From...
