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EP1C3

Altera
Part Number EP1C3
Manufacturer Altera
Description FPGA
Published Nov 8, 2019
Detailed Description April 2003, ver. 1.2 ® Cyclone FPGA Family Data Sheet Introduction Preliminary Information Features... The CycloneTM...
Datasheet PDF File EP1C3 PDF File

EP1C3
EP1C3


Overview
April 2003, ver.
1.
2 ® Cyclone FPGA Family Data Sheet Introduction Preliminary Information Features.
.
.
The CycloneTM field programmable gate array family is based on a 1.
5-V, 0.
13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM.
With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications.
Cyclone devices support various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices.
Altera also offers new low-cost serial configuration devices to configure Cyclone devices.
■ 2,910 to 20,060 LEs, see Table 1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66-MHz, 32-bit PCI standard ■ Low speed (311 Mbps) LVDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions Table 1.
Cyclone Device Features Feature EP1C3 LEs M4K RAM blocks (128 × 36 bits) Total RAM bits PLLs Maximum user I/O pins (1) 2,910 13 59,904 1 104 Note to Table 1: (1) This parameter includes global clock pins.
EP1C4 4,000 17 78,336 2 301 EP1C6 5,980 20 92,160 2 185 EP1C12 12,060 52 239,616 2 249 EP1C20 20,060 64 294,912 2 301 Altera Corporation DS-CYCLONE-1.
2 1 Cyclone FPGA Family Data Sh...


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