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LPC11A13

NXP
Part Number LPC11A13
Manufacturer NXP
Description 32-bit ARM Cortex-M0 microcontroller
Published Feb 28, 2020
Detailed Description LPC11Axx 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB SRAM, 4 kB EEPROM; configurable analog/mixed-sig...
Datasheet PDF File LPC11A13 PDF File

LPC11A13
LPC11A13

Overview
LPC11Axx 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB SRAM, 4 kB EEPROM; configurable analog/mixed-signal Rev.
4 — 30 October 2012 Product data sheet 1.
General description The LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures.
The LPC11Axx operate at CPU frequencies of up to 50 MHz.
Analog/mixed-signal subsystems can be configured by software from interconnected digital and analog peripherals.
The digital peripherals on the LPC11Axx include up to 32 kB of flash memory, up to 4 kB of EEPROM data memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I2C-bus interface, a RS-485/EIA-485 USART, two SSP controllers, four general purpose counter/timers, and up to 42 general purpose I/O pins.
Analog peripherals include a 10-bit ADC, a 10-bit DAC, an analog comparator, a temperature sensor, an internal voltage reference, and UnderVoltage LockOut (UVLO) protection.
2.
Features and benefits www.
DataSheet.
net/  System:  ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
 Serial Wire Debug (SWD)  JTAG boundary scan.
 System tick timer.
 Memory:  Up to 32 kB on-chip flash program memory.
 Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
 Up to 8 kB SRAM data memory.
 16 kB boot ROM.
 In-System Programming (ISP) for flash and In-Application Programming (IAP) for flash and EEPROM via on-chip bootloader software.
 Includes ROM-based 32-bit integer division and I2C-bus driver routines.
 Digital peripherals:  Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.
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