DSSHA1
19-5870; Rev 0; 5/11
Memory-Mapped SHA-1 Coprocessor
General Description
The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA-1 computation required for authenticating SHA-1 devices....
