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IDT5V41068A

Renesas
Part Number IDT5V41068A
Manufacturer Renesas
Description PCIE GEN1/2/3 CLOCK MULTIPLEXER
Published Aug 8, 2020
Detailed Description 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER DATASHEET IDT5V41068A Description The IDT5V41068A is a 2:1 differential clock mux ...
Datasheet PDF File IDT5V41068A PDF File

IDT5V41068A
IDT5V41068A

Overview
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER DATASHEET IDT5V41068A Description The IDT5V41068A is a 2:1 differential clock mux for PCI Express applications.
It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems.
The IDT5V41068A selects between 1 of 2 differential HCSL inputs to drive a single differential HCSL output pair.
The output can also be terminated to LVDS.
Recommended Applications • Clock muxing in PCIe Gen2 and Gen3 applications Output Features • 1 – 0.
7V current mode differential HCSL output pair Features/Benefits • Low additive jitter; suitable for use in PCIe Gen2 and Gen3 systems • 16-pin TSSOP package; small board footprint • Outputs can be terminated to LVDS; can drive a wider variety of devices • OE control pin; greater system power management • Industrial temperature range available; supports demanding embedded applications Key Specifications • Additive cycle-to-cycle jitter <5 ps • Additive phase jitter (PCIe Gen3) <0.
2ps • Operating frequency up to 200MHz Block Diagram VDD OE 3 IN1 IN1 CLK MUX IN2 2 to 1 IN2 CLK 3 SEL GND PD Rr (IREF) IDT® 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 1 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Pin Assignment VDDIN 1 DIF_IN1 2 DIF_IN1# 3 ^PD# 4 DIF_IN2 5 DIF_IN2# 6 ^OE 7 GND 8 5V41068 16 ^SEL 15 DIF_0 14 DIF_0# 13 GND 12 GND 11 VDD 10 VDD 9 IREF Note: Pins preceeded by '*^ have internal 120K ohm pull up resistors 16-pin TSSOP Select Table SEL 0 1 Outputs DIF_IN2 DIF_IN1 Pin Descriptions PIN # PIN NAME 1 VDDIN 2 DIF_IN1 3 DIF_IN1# PIN TYPE DESCRIPTION PWR Power pin for the Inputs, nominal 3.
3V IN 0.
7 V Differential TRUE input IN 0.
7 V Differential Complementary Input 4 ^PD# Asynchronous active low input pin used to power down the device.
The internal IN c locks are dis abled and the VCO and the crystal os c.
(if any) are stopped.
5 DIF_IN2 6 DIF_IN2# IN 0.
7 V Differential TRUE input IN 0.
7 V Differential Complementary Inp...


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