2.5-V Phase Lock Loop Clock Driver
Description
CDCV850, CDCV850I 2.5ĆV PHASE LOCK LOOP CLOCK DRIVER
WITH 2ĆLINE SERIAL INTERFACE
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
D Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
DGG PACKAGE (TOP VIEW)
Applications
D Spread Spectrum Clock Compatible D Operating Frequency: 60 to 140 MHz D Low Jitter (cyc−cyc): ±75 ps D Distributes One D...
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