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CS2600

Part Number	CS2600
Manufacturer	Cirrus Logic
Description	Fractional-N Clock Synthesizer and Clock Multiplier
Published	Apr 2, 2024
Detailed Description	CS2600 Fractional-N Clock Synthesizer and Clock Multiplier Features • Minimal board space required • Frequency synth...
Datasheet	CS2600 PDF File

Overview

CS2600 Fractional-N Clock Synthesizer and Clock Multiplier Features • Minimal board space required • Frequency synthesizer based on delta-sigma fractional-N analog PLL — Generates a low-jitter 6–75 MHz clock (CLK_OUT) from 8–75 MHz timing reference clock (REF_CLK) • Clock multiplier and jitter reduction based on hybrid PLL — Generates a low-jitter 6–75 MHz clock (CLK_OUT) from a jittery or intermittent 50 Hz–30 MHz input clock source (CLK_IN) • Highly accurate PLL multiplication factor — No external analog loop-filter components • Customer-programmable startup configuration, using integrated One-Time Programmable (OTP) memory • Automatic rate control for digital audio applications • BCLK and FSYNC outputs (derived from CLK_OUT) for digital audio applications can be aligned in phase with the clock source • Glitchless clock outputs derived from an intermittent input clock — Less than 1 PPM • I²C/SPI control port and hardware control mode • Configurable auxiliary output • Flexible sourcing of timing reference clock — External clock, external crystal, or built-in inductorcapacitor oscillator (LCO) Applications • Digital audio systems • Network and USB audio interfaces • IoT sensor and transducer systems • Embedded systems • Period jitter of 40 psRMS for REF_CLK and 35 psRMS for • Automotive audio systems LCO VDD GND XTI/ REF_CLK XTO/ LCO_EN CLK _I N Divider XTAL In t er fa ce LCO PLL Core Fractional‐N Analog PLL Ratio (N) Frac tiona l‐N Digital FLL Timing Reference Frequency Reference CL K_OU T BC LK FSYN C P_U nlock Indicator F_Unlock Indicator BCLK Divider FSYNC D ivider Phase Alignment Mode Controller Hardware Control I2C/SPI Control Port 123 456 I2C_AD, I2C_SCL, I2C_SDA, SPI_CS SPI_SCK SPI_SDI SPI_SDO Hardware/Software Mode Pins Demux VDD 2.
5 V LDO OTP Memory AUX CLK_OUT BCLK FSYNC SW_ EN / I2C_SCL/ SPI_SCK/ SPI_SDO/ V DD_ OT P_IN HWCONFIG1 I2C_AD/ HWCON FIG 3 SPI_CS/ I2C_SDA/ HWCONFIG5 SPI_SDI/ VDD_OTP_OUT/ HWCONFIG2 HWCON FIG 4 ...

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