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A63G7332

Part Number	A63G7332
Manufacturer	AMIC Technology
Description	128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output
Published	Mar 23, 2005
Detailed Description	A63G7332 Series 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Preliminary Docu...
Datasheet	A63G7332 PDF File

Overview

A63G7332 Series 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Preliminary Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Revision History Rev.
No.
1.
0 1.
1 2.
0 2.
1 History Initial issue Change pin 14 description from VCC to NC Change package type from 100-pin TQFP to 100-pin LQFP Change fast access times from 4.
5/5/5.
5 ns to 4.
2/4.
5/5.
0 ns Modify 100-pin LQFP symbol y dimensions Max.
in mm : 0.
08 → 0.
1 Max.
in inches : 0.
003 → 0.
004 Issue Date November, 1997 June 17, 1998 August 27, 1998 December 31, 1998 Remark Preliminary PRELIMINARY (December, 1998, Version 2.
1) AMIC Technology, Inc.
A63G7332 Series 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Preliminary Features n n n n n n Fast access times: 4.
2/4.
5/5.
0 ns (143/133/100 MHZ) Single +3.
3V+10% or +3.
3V-5% power supply Separate +2.
5V+0.
4V/-0.
12V isolated output buffer 3.
3V tolerant inputs Synchronous burst function Individual Byte Write control and Global Write n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Selectable BURST mode n SLEEP mode (ZZ pin) provided n Available in 100-pin LQFP package General Description The A63G7332 is a high-speed, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits.
The A63G7332 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output registers and a 128K X 32 SRAM core to provide a wide range of data RAM applications.
The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers.
Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE...

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A63G7332 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output - AMIC Technology

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