3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Description
Advance information
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AS4LC8M8S0 AS4LC4M16S0
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Features
PC100/133 compliant Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16) Fully synchronous - All signals referenced to positive edge of clock Four internal banks controlled by BA0/BA1 (bank select) High...
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