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ADF4210

Part Number	ADF4210
Manufacturer	Analog Devices
Description	Dual RF/IF PLL Frequency Synthesizers
Published	Mar 24, 2005
Detailed Description	a Dual RF/IF PLL Frequency Synthesizers ADF4210/ADF4211/ADF4212/ADF4213 GENERAL DESCRIPTION FEATURES ADF4210: 550 MHz/...
Datasheet	ADF4210 PDF File

Overview

a Dual RF/IF PLL Frequency Synthesizers ADF4210/ADF4211/ADF4212/ADF4213 GENERAL DESCRIPTION FEATURES ADF4210: 550 MHz/1.
2 GHz ADF4211: 550 MHz/2.
0 GHz ADF4212: 1.
0 GHz/2.
7 GHz ADF4213: 1.
0 GHz/3 GHz 2.
7 V to 5.
5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler RF and IF: 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents 3-Wire Serial Interface Analog and Digital Lock Detect Fastlock Mode Power-Down Mode The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters.
They can provide the LO for both the RF and IF sections.
They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B Counters and a dual-modulus prescaler (P/P + 1).
The A (6-bit) and B (12-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A).
In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input.
A complete PLL (PhaseLocked Loop) can be implemented if the synthesizer is used with an external loop ﬁlter and VCO (Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
APPLICATIONS The devices operate with a power supply ranging from 2.
7 V to Base Stations for Wireless Radio (GSM, PCS, DCS, 5 V and can be powered down when not in use.
CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 VP1 VP2 RSET 12-BIT IF B-COUNTER IFIN IF PRESCALER 8-BIT IF A-COUNTER PHASE COMPARATOR REFERENCE CHARGE PUMP IF CURRENT SETTING IFCP3 IFCP2 IFCP1 CPIF REFIN OSCILLATOR 14-BIT IF R-COUNTER IF LOCK DETECT CLOCK DATA LE 24-BIT DATA SDOUT REGI...

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