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HM62W8511H

Part Number	HM62W8511H
Manufacturer	Hitachi Semiconductor
Description	4M High Speed SRAM (512-kword x 8-bit)
Published	Mar 26, 2005
Detailed Description	HM62W8511H Series 4M High Speed SRAM (512-kword × 8-bit) ADE-203-750D (Z) Rev. 1.0 Sep. 15, 1998 Description The HM62W8...
Datasheet	HM62W8511H PDF File

Overview

HM62W8511H Series 4M High Speed SRAM (512-kword × 8-bit) ADE-203-750D (Z) Rev.
1.
0 Sep.
15, 1998 Description The HM62W8511H is a 4-Mbit high speed static RAM organized 512-kword × 8-bit.
It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit designing technology.
It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system.
The HM62W8511H is packaged in 400-mil 36-pin SOJ for high density surface mounting.
Features • Single supply : 3.
3 V ± 0.
3 V • Access time 12/15 ns (max) • Completely static memory  No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible  All inputs and outputs • Operating current : 150/130 mA (max) • TTL standby current : 60/50 mA (max) • CMOS standby current : 5 mA (max) : 1 mA (max) (L-version) • Data retension current : 0.
6 mA (max) (L-version) • Data retension voltage : 2 V (min) (L-version) • Center VCC and VSS type pinout HM62W8511H Series Ordering Information Type No.
HM62W8511HJP-12 HM62W8511HJP-15 HM62W8511HLJP-12 HM62W8511HLJP-15 Access time 12 ns 15 ns 12 ns 15 ns Package 400-mil 36-pin plastic SOJ (CP-36D) Pin Arrangement HM62W8511HJP/HLJP Series A0 A1 A2 A3 A4 CS I/O1 I/O2 VCC VSS I/O3 I/O4 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O8 I/O7 VSS VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC 2 HM62W8511H Series Pin Description Pin name A0 to A18 I/O1 to I/O8 CS OE WE VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Power supply Ground No connection Block Diagram (LSB) A1 A17 A7 A11 A16 A2 A6 A5 (MSB) VCC Row decoder Memory matrix 256 rows × 8 columns × 256 blocks × 8 bit (4,194,304 bits) VSS CS I/O1 .
.
.
I/O8 Column I/O Input data control Column decoder CS WE CS A10 ...

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