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DM74ALS646

Fairchild Semiconductor
Part Number DM74ALS646
Manufacturer Fairchild Semiconductor
Description Octal 3-STATE Bus Transceiver and Register
Published Apr 1, 2005
Detailed Description DM74ALS646 Octal 3-STATE Bus Transceiver and Register October 1986 Revised February 2000 DM74ALS646 Octal 3-STATE Bus ...
Datasheet PDF File DM74ALS646 PDF File

DM74ALS646
DM74ALS646

Overview
DM74ALS646 Octal 3-STATE Bus Transceiver and Register October 1986 Revised February 2000 DM74ALS646 Octal 3-STATE Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.
This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads.
The high-impedance state and increased high-logic level drive provides this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without the need for interface or pull-up components.
They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The registers in the DM74ALS646 are edge-triggered Dtype flip-flops.
On the positive transition of the clock (CAB or CBA), the input bus data is stored into the appropriate register.
The CAB input controls the transfer of data into the A register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred.
A LOW input level selects real-time data, and a HIGH level selects stored data.
The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between store and real-time data.
The enable G and direction control pins provide four modes of operation: real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internally stored data transfer to bus A or B.
When the enable G pin is LOW, the direction pin selects which bus receives data.
When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled.
Features s Switching specifica...


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