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74ACTQ544

Fairchild Semiconductor
Part Number 74ACTQ544
Manufacturer Fairchild Semiconductor
Description Quiet Series Octal Registered Transceiver
Published Apr 3, 2005
Detailed Description 74ACQ544 • 74ACTQ544 Quiet Series Octal Registered Transceiver with 3-STATE Outputs March 1990 Revised September 2000 ...
Datasheet PDF File 74ACTQ544 PDF File

74ACTQ544
74ACTQ544

Overview
74ACQ544 • 74ACTQ544 Quiet Series Octal Registered Transceiver with 3-STATE Outputs March 1990 Revised September 2000 74ACQ544 • 74ACTQ544 Quiet Series Octal Registered Transceiver with 3-STATE Outputs General Description The ACQ/ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction.
Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow.
The 544 inverts data in both directions.
The ACQ/ACTQ utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance.
FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s 8-bit inverting octal latched transceiver s Separate controls for data flow in each direction s Back-to-back registers for storage s Outputs source/sink 24 mA Ordering Code: Order Number 74ACQ544SC 74ACQ544SPC 74ACTQ544SC 74ACTQ544SPC Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.
300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.
300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
300 Wide Device also available in Tape and Reel.
Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0 –A7 Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data...


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