DatasheetsPDF.com

74F109

Dual JK Positive Edge-Triggered Flip-Flop

Description

74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operatio...

Fairchild Semiconductor

74F109 PDF File

Similar Datasheet

74F10 Triple 3-input NAND gate - NXP
74F10 Triple 3-Input NAND Gate - Fairchild Semiconductor
74F10 Triple 3-Input NAND Gate - National Semiconductor
74F10 TRIPLE 3-INPUT POSITIVE-NAND GATE - Texas Instruments
74F1056 8-Bit Schottky Barrier Diode Array - Fairchild Semiconductor
74F1071 18-Bit Undershoot/Overshoot Clamp - Fairchild Semiconductor
74F109 Dual JK Positive Edge-Triggered Flip-Flop - National Semiconductor
74F109 Positive J-K positive edge-triggered flip-flops - NXP
74F109 Dual JK Positive Edge-Triggered Flip-Flop - Fairchild Semiconductor
74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP - Texas Instruments

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)