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74F113

Part Number	74F113
Manufacturer	NXP
Description	Dual J-K negative edge-triggered flip-flops
Published	Apr 3, 2005
Detailed Description	INTEGRATED CIRCUITS 74F113 Dual J-K negative edge-triggered flip-flops without reset Product specification IC15 Data Ha...
Datasheet	74F113 PDF File

Overview

INTEGRATED CIRCUITS 74F113 Dual J-K negative edge-triggered flip-flops without reset Product specification IC15 Data Handbook 1991 Feb 14 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flops without reset 74F113 FEATURE • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs.
The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs.
A high level on the clock (CP) input ...

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