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IDT54FCT162652T

Integrated Device Technology
Part Number IDT54FCT162652T
Manufacturer Integrated Device Technology
Description FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS
Published Apr 3, 2005
Detailed Description FAST CMOS 16-BIT BUS IDT54/74FCT16652T/AT/CT/ET IDT54/74FCT162652T/AT/CT/ET TRANSCEIVER/ REGISTERS Integrated Device Tec...
Datasheet PDF File IDT54FCT162652T PDF File

IDT54FCT162652T
IDT54FCT162652T

Overview
FAST CMOS 16-BIT BUS IDT54/74FCT16652T/AT/CT/ET IDT54/74FCT162652T/AT/CT/ET TRANSCEIVER/ REGISTERS Integrated Device Technology, Inc.
FEATURES: • Common features: – 0.
5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions – Typical tSK(o) (Output Skew) < 250ps – Low input and output leakage ≤1µ A (max.
) – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – Packages include 25 mil pitch SSOP, 19.
6 mil pitch TSSOP,15.
7 mil pitch TVSOP and 25 mil pitch Cerpack – Extended commercial range of -40°C to +85°C – VCC = 5V ±10% • Features for FCT16652T/AT/CT/ET: – High drive outputs (-32mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” – Typical VOLP (Output Ground Bounce) < 1.
0V at VCC = 5V, TA = 25°C • Features for FCT162652T/AT/CT/ET: – Balanced Output Drivers: ±24mA (commercial), ±16mA (military) – Reduced system switching noise – Typical VOLP (Output Ground Bounce) < 0.
6V at VCC = 5V,TA = 25°C DESCRIPTION: The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET 16-bit registered transceivers are built using advanced dual metal CMOS technology.
These high-speed, low-power de- vices are organized as two independent 8-bit bus transceivers with 3-state D-type registers.
For example, the xOEAB and xOEBA signals control the transceiver functions.
The xSAB and xSBA control pins are provided to select either real time or stored data transfer.
The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real time data.
A LOW input level selects real-time data and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the select or enable control pins.
Flow-through organization of signal pins simplifies layout.
All inputs are designed with hysteresis for improved n...


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