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K4S281632D-NL75

Part Number	K4S281632D-NL75
Manufacturer	Samsung semiconductor
Description	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Published	Apr 7, 2005
Detailed Description	K4S281632D CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Rev. 0.1 Sept. 2001 * Samsung Electr...
Datasheet	K4S281632D-NL75 PDF File

Overview

K4S281632D CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Rev.
0.
1 Sept.
2001 * Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
1 Sept.
2001 K4S281632D Revision History Revision 0.
0 (Mar.
06, 2001) Revision 0.
1 (Sep.
06, 2001) • • CMOS SDRAM Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter.
< Before > 5.
For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
< After > 5.
In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev.
0.
1 Sept.
2001 K4S281632D 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) Part No.
K4S281632D-TC/L55 K4S281632D-TC/L60 K4S281632D-TC/L7C K4S281632D-TC/L75 K4S281632D-TC/L1H K4S281632D-TC/L1L CMOS SDRAM GENERAL DESCRIPTION The K4S281632D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION Max Freq.
183MHz(CL=3) 166MHz(CL=3) 133MHz(CL=2) 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54 TSOP(II) Interface P...

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