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K4S511632B-TCL75

Samsung semiconductor
Part Number K4S511632B-TCL75
Manufacturer Samsung semiconductor
Description 512Mb B-die SDRAM Specification
Published Apr 7, 2005
Detailed Description SDRAM 512Mb B-die (x4, x8, x16) CMOS SDRAM 512Mb B-die SDRAM Specification Revision 1.1 February 2004 * Samsung Elec...
Datasheet PDF File K4S511632B-TCL75 PDF File

K4S511632B-TCL75
K4S511632B-TCL75

Overview
SDRAM 512Mb B-die (x4, x8, x16) CMOS SDRAM 512Mb B-die SDRAM Specification Revision 1.
1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice.
Rev.
1.
1 February 2004 SDRAM 512Mb B-die (x4, x8, x16) Revision History Revision 1.
0 (January, 2004) - First release.
Revision 1.
1 (February, 2004) - Corrected typo.
CMOS SDRAM Rev.
1.
1 February 2004 SDRAM 512Mb B-die (x4, x8, x16) CMOS SDRAM 32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8) -.
Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (8K Cycle) GENERAL DESCRIPTION The K4S510432B / K4S510832B / K4S511632B is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 4 bits / 4 x 16,777,216 words by 8 bits / 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information Part No.
K4S510432B-TC(L)75 K4S510832B-TC(L)75 K4S511632B-TC(L)75 Orgainization 128Mb x 4 (CL=3) 64Mb x 8 (CL=3) 32Mb x 16 (CL=3) Max Freq.
133MHz 133MHz 133MHz LVTTL 54pin TSOP(II) Interface Package Organization 128Mx4 64Mx8 32Mx16 Row Address A0~A12 A0~A12 A0~A12 Column Address A0-A9, A11, A12 A0-A9, A11 A0-A9 Row & Column address configuration Rev.
1.
1 February 2004 SDRAM 51...


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