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SAB9079HS

Part Number	SAB9079HS
Manufacturer	NXP
Description	Multistandard Picture-In-Picture PIP controller
Published	Apr 8, 2005
Detailed Description	INTEGRATED CIRCUITS DATA SHEET SAB9079HS Multistandard Picture-In-Picture (PIP) controller Preliminary speciﬁcation Fi...
Datasheet	SAB9079HS PDF File

Overview

INTEGRATED CIRCUITS DATA SHEET SAB9079HS Multistandard Picture-In-Picture (PIP) controller Preliminary speciﬁcation File under Integrated Circuits, IC02 2000 Jan 13 Philips Semiconductors Preliminary speciﬁcation Multistandard Picture-In-Picture (PIP) controller FEATURES • Suitable for single PIP, double window and multi PIP applications • Data formats 4 : 1 : 1 (all modes) and 4 : 2 : 2 (most modes) • Sample rate of 14 MHz, 720 Y*-pixels/line • Horizontal reduction factors 1⁄1 3⁄4, 2⁄3, 1⁄2, 1⁄3, 1⁄4 and 1⁄6 • Vertical reduction factors 1⁄ , 1⁄ , 1⁄ 1 2 3 SAB9079HS GENERAL DESCRIPTION The SAB9079HS is a PIP controller for a multistandard application environment in combination with a multistandard decoder such as for example TDA8310, TDA9143 or TDA9321H.
The SAB9079HS inserts one or two live video signals with reduced sizes into the main/display video signal.
All video signals are expected to be analog baseband signals.
The analog signals are stripped signals without sync.
Therefore the luminance signal is referred to as Y*.
The conversion into the digital environment and back is done on-chip as well as the internal clock generation.
The SAB9079HS is suitable for single PIP, double window and multi PIP applications.
and 1⁄ 4 • PIP OSD for the sub channels displayed • Detection of PAL/NTSC with overrule bit • CTE/LTE like circuits in display part • Replay with definable auto increment, picture sample rate and picture number auto wrap • Programmable Y*UV to RGB conversion matrix with independent coefficients for NTSC and PAL sources • Display clock and synchronisation are derived from the main PLL • Three 8-bit Digital-to-Analog Converters (DACs) • Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit performance) with clamp circuit for each acquisition channel • Main and sub can write to the same VDRAM address spaces under certain conditions; the reduction factors should be the same • Y* and UV pedestals on the acquisition sides • Independent vertical fil...

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