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PC74HC594P

NXP
Part Number PC74HC594P
Manufacturer NXP
Description 8-bit shift register with output register
Published Mar 22, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Fam...
Datasheet PDF File PC74HC594P PDF File

PC74HC594P
PC74HC594P

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT594 8-bit shift register with output register Product specification File under Integrated Circuits, IC06 December 1991 Philips Semiconductors Product specification 8-bit shift register with output register FEATURES • Synchronous serial input and output • 8-bit parallel output • Shift and storage register have independent direct clear and clocks • 100 MHz (typ.
) • Output capability: – parallel outputs: bus driver – serial outputs: standard • ICC category: MSI APPLICATIONS • Serial-to parallel data conversion • Remote control holding register DESCRIPTION 74HC/HCT594 The 74HC/HCT594 are high-speed, Si-gate CMOS devices, and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard No.
7A.
The 74HC/HCT594 contain an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
Separate clocks and direct overriding clears are provided on both the shift and storage registers.
A serial output (Q7’) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered.
If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register.
QUICK REFERENCE DATA GND = 0 V: Tamb = 250 C; tr = tf = 6 ns.
TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay SHCP to Q7’ STCP to Qn SHR to Qn STR to Qn fmax CI CPD Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo), where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of the outputs; CL = output load capacitance in pF; VCC = supply voltage in V.
2.
For HC, the condition is VI = GND to...


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