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TC74VHC573F

Toshiba
Part Number TC74VHC573F
Manufacturer Toshiba
Description Octal D-Type Latch
Published Apr 23, 2005
Detailed Description TC74VHC573F/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC573F, TC74VHC573FK Octal D-Type Latch w...
Datasheet PDF File TC74VHC573F PDF File

TC74VHC573F
TC74VHC573F

Overview
TC74VHC573F/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC573F, TC74VHC573FK Octal D-Type Latch with 3-State Output The TC74VHC573 is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input ( OE ).
When the OE input is high, the eight outputs are in a high impedance state.
An input protection circuit ensures that 0 to 5.
5 V can be applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
Features  High speed: tpd = 4.
5 ns (typ.
) at VCC = 5 V  Low power dissipation: ICC = 4 A (max) at Ta = 25°C  High noise immunity: VNIH = VNIL = 28% VCC (min)  Power down protection is provided on all inputs.
 Balanced propagation delays: tpLH tpHL  Wide operating voltage range: VCC (opr) = 2 to 5.
5 V  Low noise: VOLP = 1.
0 V (max)  Pin and function compatible with 74ALS573 TC74VHC573F TC74VHC573FK Weight SOP20-P-300-1.
27A VSSOP20-P-0030-0.
50 : 0.
22 g (typ.
) : 0.
03 g (typ.
) © 2019 1 Toshiba Electronic Devices & Storage Corporation Start of commercial production 1991-11 2019-01-31 Pin Assignment IEC Logic Symbol TC74VHC573F/FK 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10 (top view) 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE (1) EN LE (11) C1 D0 (2) 1D D1 (3) D2 (4) D3 (5) D4 (6) D5 (7) D6 (8) D7 (9) (19) Q0 (18) Q1 (17) Q2 (16) Q3 (15) Q4 (14) Q5 (13) Q6 (12) Q7 Truth Table Inputs OE LE D H X X L L X L H L L H H Output Z Qn L H X: Don’t care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low...


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