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EI68C153

IMP
Part Number EI68C153
Manufacturer IMP
Description Bus Interrupter Module (VME)
Published Apr 23, 2005
Detailed Description Ei68C153 Bus Interrupter Module (VME) Semiconductor, Inc. FEATURES • • • • • • Programmable interrupt controller for VM...
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EI68C153
EI68C153

Overview
Ei68C153 Bus Interrupter Module (VME) Semiconductor, Inc.
FEATURES • • • • • • Programmable interrupt controller for VMEbus and VERSAbus ™ systems Receives and prioritizes 4 independent local interrupt sources 7 programmable interrupt request levels for each local interrupt source Separate control and vector registers for each local interrupt source Interrupt enable and interrupt clear bits Two response modes: Internal (vectored mode) or external (interrupting device-sup plies-the-vector mode) Interrupt acknowledge daisy chain Flag bits with auto-clear capability Pin & function compatible with Motorola MC68153 Single 5.
0 volt power supply Advanced CMOS low-power technology DESCRIPTION The Bus Interrupter Module (BIM) provides an interface between interrupting devices and a system bus such as the VMEbus or VERSAbus™.
It generates a maximum of 7 bus interrupts on the IRQ1-IRQ7 outputs and responds to interrupt acknowledge cycles for up to 4 independent slaves.
The BIM can also supply an interrupt vector during an interrupt acknowledge cycle.
Moreover, it sits in the interrupt acknowledge daisychain which allows for multiple interrupts on the level acknowledged.
The BIM accepts device interrupt requests on inputs INT0, INT1, INT2 and INT3.
Each input is regulated by Bit 4 (IRE) of the associated control register (CRO controls INT0, CR! controls INT1,etc.
).
If IRE (Interrupt Enable) is set and a device input is asserted, an Interrupt Request open-collector output (IRQ1 - IRQ7) is asserted.
The asserted IRQX output is selected by the value programmed in Bits 0, 1, and 2 of the control register (L0, L1, and L3).
This 3-bit field determines the interrupt request level as set by software.
Two or more interrupt sources can be programmed to the same request level.
The corresponding IRQX output will remain asserted until multiple interrupt acknowledge cycles respond to all requests.
If the interrupt request level is set to zero, the interrupt is disabled because there is no ...


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