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M54HC323

Part Number	M54HC323
Manufacturer	ST Microelectronics
Description	8-BIT PIPO SHIFT REGISTER
Published	Apr 23, 2005
Detailed Description	M54/74HC299 M54/74HC323 HC299 8 BIT PIPO SHIFT REGISTER WITHASYNCHRONOUS CLEAR HC323 8 BIT PIPO SHIFT REGISTER WITH SYNC...
Datasheet	M54HC323 PDF File

Overview

M54/74HC299 M54/74HC323 HC299 8 BIT PIPO SHIFT REGISTER WITHASYNCHRONOUS CLEAR HC323 8 BIT PIPO SHIFT REGISTER WITH SYNCHRONOUS CLEAR .
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HIGH SPEED fMAX = 42 MHz (TYP.
) AT VCC = 5V LOW POWER DISSIPATION ICC = 4 µA (MAX.
) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.
) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS FOR QA’ TO QH’ 15 LSTTL LOADS FOR QA TO QH SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 6 mA (MIN.
) FOR Q A, TO QH, IOH = IOL = 4 mA (MIN.
) FOR Q A, TO QH BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS299 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC299/323 are high speed CMOS 8BIT PIPO SHIFT REGISTERS (3-STATE) fabricated with silicon gate C2MOS technology.
They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power consumption.
These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA).
Each mode is chosen by two function select inputs (S0, S1).
When one or both enable inputs, (G1, G2) are high, the eight input/output terminals are in the highimpedance state ; however sequential operation or clearing of the register is not affected.
Clear function on the HC299 is asynchronous to CLOCK, while the HC323 is cleared synchronous to clock.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
October 1993 NC = No Internal Connection 1/15 M54/M74HC299/323 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS MODE CLEAR L L L H H H H H H FUNCTION SELECTED S1 Z CLEAR HOLD SHIFT RIGHT SHIFT LEFT LOAD H L X L L L H H H S0 H X L L H H L L H OUTPUT CONTROL G1 * X L L L L L L L X G2 * X L L L L L L L X CLOCK (299) X X X X (323) INPUTS/OUTPUTS SERIAL SL X X X X X X H L X SR X X X X H L X X X Z ...

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