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M54HC76

Part Number	M54HC76
Manufacturer	ST Microelectronics
Description	DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
Published	Apr 26, 2005
Detailed Description	M54HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 65 MHz (TYP.) AT VCC = 5 V ...
Datasheet	M54HC76 PDF File

Overview

M54HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR .
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HIGH SPEED fMAX = 65 MHz (TYP.
) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.
) AT 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.
) BALANCED PROPAGATION DELAYS tPLH = tPHL HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.
) WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS76 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC76F1R M74HC76M1R M74HC76B1R M74HC76C1R DESCRIPTION The M54/74HC76 is a high speed CMOS DUAL J-K FLIP FLOP fabricated in silicon gate C 2MOS technology.
It has the same high speed performance of LSTTL combined with true CMOS low power consumption.
Depending on with the logic level at the J and K inputs this device changes state on the negative going transition of the clock pulse.
CLEAR and PRESET are independent of the clock and are accomplished by a logic low on the corresponding input.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No Internal Connection October 1992 1/11 M54/M74HC76 TRUTH TABLE INPUTS CLR L H L H H H H H X: Don’t Care OUTPUTS K X X X L H L H X CK X X X Q L H H Qn L H Qn Qn Q H L H Qn H L Qn Qn PR H L L H H H H H J X X X L L H H X FUNCTION CLEAR PRESET NO CHANGE TOGGLE NO CHANGE PIN DESCRIPTION PIN No 1, 6 2, 7 3, 8 4, 9 10, 14 11, 15 16, 12 5 13 SYMBOL 1CK, 2CK 1PR, 2PR 1CLR, 2CLR 1J, 2J 1Q, 2Q 1Q, 2Q 1K, 2K GND V CC NAME AND FUNCTION Clock Input (HIGH to LOW edge triggered) Set Inputs (Active LOW) Asynchronous Reset Inputs (Active LOW) Data Inputs: Flip-Flop 1 and 2 Complement Flip-Flop Outputs True Flip-Flop Outputs Data Inputs: Flip-Flop 1 and 2 Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL LOGIC DIAGRAM (1/2 Package) 2/11 M54/M74HC76 ABSOLUTE MAXIMUM RA...

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