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M2S56D20TP

Part Number	M2S56D20TP
Manufacturer	Mitsubishi
Description	256M Double Data Rate Synchronous DRAM
Published	May 2, 2005
Detailed Description	DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM PRELIM...
Datasheet	M2S56D20TP PDF File

Overview

DDR SDRAM (Rev.
0.
0) Sep.
'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice.
DESCRIPTION M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface.
All control and address signals are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK.
The M2S56D20/30 TP achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES - Vdd=Vddq=2.
5v±0.
2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 1.
5/2.
0/2.
5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8) - SSTL_2 Interface - 400-mil, 66-pin Thin Small Outline Package (TSOP II) - FET switch control(/QFC) - JEDEC standard PIN CONFIGURATION (TOP VIEW) x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 66pin TSOP(II) 7 8 9 10 11 12 13 400mil width x 14 15 875mil length 16 17 18 19 0.
65mm 20 Lead Pitch 21 22 23 24 25 ROW 26 A0-12 27 Column 28 A0-9,11(x4) 29 A0-9 (x8) 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 3...

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